Student Publication

2022

 

2. Impact of Trap Charge effects on the Performance of 2D material-based FET Sinjini Misra;Swastik Dhar;Ayush Sarkar;Swapnendu Sarkar;Anada Sankar Chakraborty;Swarnil Roy;Sudipta Ghosh 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)


3. DC and Analog/RF Performance Analysis of Gate-Drain Underlapped and Channel Engineered TFET Sudipta Ghosh;Sayan Bose;Wahid Anwar;Madhusree Banerjee;P. Venkateswaran;Subir Kumar Sarkar 2022 IEEE VLSI Device Circuit and System (VLSI DCS)

 

4. Impact of Trap Charge effects on the Performance of 2D material-based FET Sinjini Misra;Swastik Dhar;Ayush Sarkar;Swapnendu Sarkar;Anada Sankar Chakraborty;Swarnil Roy;Sudipta Ghosh 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)

 

5. A super Threshold Compact Silicon Neuron Circuit for Different Neuron Dynamics Suitable for Spiking Neural Network Sayantan Samanta;Koushik Naskar;Souvanik Pal;Suman Mallik;Sudipta Ghosh;Swarnil Roy 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)


2021

2.  Analytical modeling of Linearity and Intermodulation distortion of 3D Gate All Around Junctionless (GAA - JL) FET, Ankush Chattopadhyay, Manash Chanda, Chayanika Bose, C. K. Sarkar, Superlattices and Microstructures, 2021, https://doi.org/10.1016/j.spmi.2020.106788

3.  Analysis of Harmonic Distortions in GAA Junctionless FET using Analytical Model for reliable low power applications, Ankush Chattopadhyay, Manash Chanda, Chayanika Bose, C. K. Sarkar, Journal of Electronic Materials, Springer, 2021


2020

1.      Dipanjan Sen, Savio Sengupta, Manash Chanda, Swarnil.Roy (2020). Analysis of D.C Parameters of Short-Channel Heterostructure Double Gate Junction-Less MOSFET Circuits Considering Quantum Mechanical Effects. Silicon, Springer, DOI: 12. 10.1007/s12633-020-00507-0.

2.      Mainak Mukhrjee, Manash Chanda and Angsuman Sarkar and Anup Dey, “Effect of band non-parabolicity on energy sub-band profile for nano-dimensional MOSFET”, Journal of Microsystem Technologies, Springer, pp. 1-8, Feb, 2020. [SCI, Impact factor: 1.6] DOI: 10.1007/s00542-020-04761-5.

3.      Ruben Ray, Rahul Das and Manash Chanda, “Effect of fringing field capacitances in RF and small signal parameters of surrounding gate MOSFET” Journal of Microsystem Technologies, Springer, Feb, 20120 . [SCI, Impact factor: 1.6], DOI: 10.1007/s00542-020-04765-1

4.      Amit Bhattacharyya;Adrija Mukherjee; Manash Chanda; Debashis De, “Advantages of Charge Plasma Based Double Gate Junctionless MOSFET Over Bulk MOSFET for Label Free Biosensing”, IEEE 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 18-19 July 2020, Kolkata, India.

5.      Adrija Mukherjee; Baishali Ray; Debankan Das; Shaon Bhattacharyya; Papiya Debnath and Manash Chanda, “Impact of Temperature on Circuit Performances of Junctionless MOSFET in Sub-threshold Regime”, IEEE 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 18-19 July 2020, Kolkata, India.


8.      S. Halder, R. Paul and S. Roy, "Design and Analysis of Bulk and Junctionless MOSFET Based Circuits for Low Power Applications," 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 2020, pp. 1-5, doi: 10.1109/VLSIDCS47293.2020.9179929.

9.      M. Mukherjee, H. Saha and S. Roy, "Investigation of Comparator Architectures in 32 nm Silicon-On-Insulator(SOI) Technology," 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 2020, pp. 34-37, doi: 10.1109/VLSIDCS47293.2020.9179914.


10.  Avtar Singh, Saurabh Chaudhury, Manash Chanda and Chandan Kumar Sarkar, “Split gated silicon nanotube FET for bio-sensing applications”, IET Circuit, Device and System, 23rd Nov 2020, Early Access, DOI: 10.1049/iet-cds.2020.0208 .

11.  Swarnil Roy, Gargi Jana and Manash Chanda, “Analysis of Sub-Threshold Adiabatic Logic Model Using Junctionless MOSFET for Low Power Application”, Silicon, Springer Nature B.V. 2020, Accepted For Publication. DOI: http://dx.doi.org/10.1007/s12633-020-00870-y

12.  H. Banerjee, K. Sarkar, P. Debnath, S. Roy and M. Chanda, "Design and Analysis of Double Gate Tunnel Field Effect Transistor using Charged Plasma," 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 2020, pp. 1-5, doi: 10.1109/VLSIDCS47293.2020.9179948.


13.  Sourav Guha, PrithvirajPachal, Sudipta Ghosh, Subir Kumar Sarkar,“Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance”, Superlattices and Microstructures, Volume 146, 2020, ISSN 0749-6036, doi.org/10.1016/j.spmi.2020.106657.

14.  S. Ghosh, P. Pachal, R. Kumar, S. Kundu, J. Ghosh and S. K. Sarkar, "Performance enhancement of p-n-p-n TFET with spacer induced hetero-dielctric gate oxide" 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), Kolkata, India, 2020, pp. 1-5, doi: 10.1109/VLSIDCS47293.2020.9179943.

15.  S. Ghosh, S. Kundu, S. Guha, J. Ghosh, P. Pachal and S. K. Sarkar, "Effect of Body Thickness on Device Performance of Graded Channel Tri-Metal Double Gate Stack Gate TFET," 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), Kolkata, India, 2020, pp. 427-431, doi: 10.1109/VLSIDCS47293.2020.9179899.


16.  Dipanjan Sen, Savio Sengupta, Manash Chanda, Swarnil.Roy (2020). Analysis of D.C Parameters of Short-Channel Heterostructure Double Gate Junction-Less MOSFET Circuits Considering Quantum Mechanical Effects. Silicon, Springer, DOI: 12. 10.1007/s12633-020-00507-0.

17.  Mainak Mukhrjee, Manash Chanda and Angsuman Sarkar and Anup Dey, “Effect of band non-parabolicity on energy sub-band profile for nano-dimensional MOSFET”, Journal of Microsystem Technologies, Springer, pp. 1-8, Feb, 2020. [SCI, Impact factor: 1.6] DOI: 10.1007/s00542-020-04761-5.

18.  Ruben Ray, Rahul Das and Manash Chanda, “Effect of fringing field capacitances in RF and small signal parameters of surrounding gate MOSFET” Journal of Microsystem Technologies, Springer, Feb, 20120 . [SCI, Impact factor: 1.6], DOI: 10.1007/s00542-020-04765-1


2019

1. Arighna Basak, Manash Chanda and Angsuman Sarkar, “Drain current modelling of unipolar junction dual material double-gate MOSFET (UJDMDG) for SoC applications”, Journal of Microsystem Technologies, Springer, Nov, 2019, . [SCI, Impact factor: 1.6], doi.org/10.1007/s00542-019-04691-x

2. Dipanjan Sen, Savio Sengupta, Manash Chanda, Swarnil.Roy, “Analytical Modeling of D.C Parameters of Double Gate Junctionless MOSFET in Near & Subthreshold Regime for RF Circuit Application”, Nanoscience and Nanotechnology – Asia, Bentham Science, July-2019. DOI: 10.2174/2210681209666190730170031

3. Savio Jay Sengupta, Dipanjan Sen, Swarnil Roy, Manash Chanda, and Subir Kumar Sarkar , “D.C. Performance Analysis of High-K Adiabatic Logic Circuits in Sub-Threshold Regime for RF Applications”, Sensor Letter, American Scientific Publisher, vol. 17, pp. 487–496 (2019).

4. D.Sen, S.J .Sengupta, S.Roy, M.Chanda, S.K.Sarkar " D.C Performance Analysis of Sub-Threshold Source-Coupled Logic Circuit Using Double Gate Junction-Less MOSFET for Low-Power Application" Sensor Letter, American Scientific Publisher, 17, no. 7, pp. 538– 545, 2019.

5. Gargi Jana, Dipanjan Sen and Manash Chanda, “ Junctionless double gate non-parabolic variable barrier height Si-MOSFET for energy efficient application”, Journal of Microsystem Technologies, Springer, pp. Nov, 2019, . [SCI, Impact factor: 1.6], DOI: 10.1007/s00542-019-04688-6

6. Sen, Dipanjan& Sengupta, Savio & Roy, Swarnil & Chanda, Manash& Sarkar, Subir. (2019). Analytical Modeling of D.C Parameters of Double Gate Junctionless MOSFET in Near & Subthreshold Regime for RF Circuit Application. Nanoscience and Nanotechnology - Asia. 09. 10.2174/2210681209666190730170031.

7. Sengupta, Savio & Sen, Dipanjan& Roy, Swarnil & Chanda, Manash& Sarkar, Subir. (2019). D.C. Performance Analysis of High-K Adiabatic Logic Circuits in Sub-Threshold Regime for RF Applications. Sensor Letters. 17. 487–496. 10.1166/sl.2019.4102.

8. M. Sen, A. Gatait, S. Ghosh, M. Chanda and A. Sarkar, “Verilog-A Modeling of Junction-less MOSFET in Sub- Threshold Regime for Ultra Low-Power Application”, IEEE WITCON ECE 2019, will be included in IEEE.

9. Amit Bhattacharyya; PrithvirajPachal; Anirban Pradhan; Manash Chanda; Debashis De, “Performance Analysis of Underlap Double Gate Oxide Stacked Junctionless MOSFET for Analog and RF Applications”, IEEE 2019 International Conference on Microwave Integrated Circuits, Photonics and Wireless Networks (IMICPW), 22-24 May 2019, DOI: 10.1109/IMICPW.2019.8933249

10. M. Sen, A. Gatait, S. Ghosh, M. Chanda, S. Roy and P. Debnath, "Verilog-A Modeling of Junction-less MOSFET in Sub- Threshold Regime for Ultra Low-Power Application," 2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE), 2019, pp. 172-176, doi: 10.1109/WITCONECE48374.2019.9092930.

11. Swarnil Roy; Sagar Mukherjee; ArkaDutta; Chandan Sarkar; Chayanika Bose “Circuit Performance Analysis of Graded Doping of Channel of DGMOS with High-k Gate Stack for Analog and Digital Application” in IET Circuits, Devices & Systems, vol. 13, no. 3, pp. 337-343, 5 2019, doi: 10.1049/iet-cds.2018.5199.


2018


1. Rahul Das, Manash Chanda, Chandan K Sarkar,“Analyticalmodeling of charge plasma based optimized nanogap embedded surrounding gate MOSFET for label free biosensing”,IEEE Transaction on Electron Device,vol. 65, issue 12, pp. 5487-5493, Oct 2018.( DOI: 10.1109/TED.2018.2872466)

 

2. Gargi Jana, Madhuchhanda Majumdar Manash Chanda, Chandan K. Sarkar4, “Analysis of Gate misalignment Effects in Double Gate Junctionless MOSFET”, accepted in IEEE ICACCT 2018, pp. 122-125, India, (included in IEEE Xplore).

3. Savio Jay Sengupta, Samarthi Chakraborty, Tamal Sarkar, Md. Zishan Iqbal and Manas Chanda,”Effect of High -K Dielectric on the Performances of Adiabatic Logic Circuits in Sub -threshold Regime”, Accepted in IEEE EDKCON 2018,included in IEEE Explore.

4. Gargi Jana and Manash Chanda, “Analytical Modeling of Drain Current of Junctionless Double Gate Si - MOSFET having Variable BarrierHeight Considering Band Non -Parabolicity”, Accepted in IEEE EDKCON 2018, included in IEEE Explore.

5. Ruben Ray, Sagnik Ghoshal and Manash Chanda, “Small Signal Modeling of Cylindrical/Surrounding Gate MOSFET for RF Application Incorporating Fringing Effect”,Accepted in IEEE EDKCON 2018, included in IEEE Explore.

 

6. D. Sen, S. J. Sengupta and S. Roy, "Study of Power Delay Characteristic of Subthreshold SCL Inverter Using Junction-Less DG-MOSFET," 2018 IEEE Electron Devices Kolkata Conference (EDKCON), Kolkata, India, 2018, pp. 455-460, doi: 10.1109/EDKCON.2018.8770417.

 

7. Manash Chanda, Sandipta Mal, Akash Mondal, Chandan Kumar Sarkar "Design and Analysis of a Logic Model for Ultra Low Power Near Threshold Adiabatic Computing", IET Circuits Devices & Systems, vol. 12, issue 4, pp. 439-446, February 2018. (DOI: DOI: 10.1049/iet-cds.2017.0347).

8. Savio Jay Sengupta, Samarthi Chakraborty, Tamal Sarkar, Md. Zishan Iqbal and Manas Chanda,”Effect of High -K Dielectric on the Performances of Adiabatic Logic Circuits in Sub -threshold Regime”, Accepted in IEEE EDKCON 2018,included in IEEE Explore.

 

9. Mainak Mukherjee, Manash Chanda, Anup Dey and AngsumanSarkar,”Effect of Band Parabolicity on Energy Sub -Band Profile for Nano - Dimensional Junctionless Metal Oxide Semiconductor Field Effect Transistors” Accepted in IEEE EDKCON 2018, included in IEEE Explore.

10. “Design and implementation of highly secured arduino based voting machine” by Santosh Kumar Shaw, SashankPoddar,Vivek Singh and Sudip Dogra published in IEEE EDKCON 2018 held at The Pride Hotel, Kolkata, 24th -25th November,2018 .

11. “Design and Development of Automatic RFID based system for Identification and separation of plastic waste using near infrared reflectance spectroscopy” by Santosh Kumar Shaw, SashankPoddar,Vivek Singh and Sudip Dogra published in IEEE EDKCON 2018 held at The Pride Hotel, Kolkata, 24th -25th November,2018 .

12. “Infrared based sensor to prevent car and motor vehicle accidents” by N. Karmakar, A. Chatterjee, K. Langal and Sudip Dogra published in IEEE EDKCON 2018 held at The Pride Hotel, Kolkata, 24th -25th November,2018 .

13. “Access control management using password protected door and selective switching for electronic gadgets using RFID technology” by A. Pradhan, S. Sarkar, G.De, K. Langal  and Sudip Dogra published in IEEE EDKCON 2018 held at The Pride Hotel, Kolkata, 24th -25th November,2018 .

14. “Water level indicator and automatic tank controller system for domestic applicatins” by A. Hore, A. Mukherjee, A. Chatterjee, K. Langal and Sudip Dogra published in IEEE EDKCON 2018 held at The Pride Hotel, Kolkata, 24th -25th November,2018 .

15. S. Ghosh, S. Nath, R. Biswas, P. Venkateswaran, J. K. Sing and S. K. Sarkar, "PSO Variants and its Comparison with Firefly Algorithm in Solving VLSI Global Routing Problem," 2018 IEEE Electron Devices Kolkata Conference (EDKCON), Kolkata, India, 2018, pp. 513-518, doi: 10.1109/EDKCON.2018.8770397.


16. JoyantoRoychoudhary, Neeraj Kr., PushpenduKanjilalPHASED ARRAY ANTENNA ADAPTIVE BEAMFORMING FOR SPACE-TIME SIGNAL PROCESSING USING HYBRID GENETIC ALGORITHMS WITH MUTATION OPERATOR APPLIED TO RAYLEIGH FADING CHANNELS, International Journal of Electronics and Communication Engineering and Technology (IJECET). Vol. 3, Issue. 9, pp. 36-46, August – 2018 ISSN No: ISSN Print: 0976-6464 and ISSN Online: 0976-6472 © IAEME Publication.

17. JoyantoRoychoudhary,Neeraj Kr.,PushpenduKanjilalLinear Antenna Array Adaptive Beam forming For Space-Time Signal Processing Using Hybrid Genetic Algorithms Applied to Fading Channels, International Journal of Computer Engineering and Sciences Research. Vol. 01, Issue. 01, pp. 01-12, October – 2018. ISSN No: 0213-4465.

18. JoyantoRoychoudhary, ArindrajitChaudhury,Neeraj Kr. Smart Antenna Array Adaptive Beamforming for Space-Time Signal Processing Using Hybrid Ga-Pso Culled Mutation Operator Using A Novel Adaptive Equalizer Applied to Fading Channels, IEEE-ICIETS,Mysuru. September – 2018 ISBN No: ISSN-2349-5162

 

19. Swapnadip De, Mainak Bhattacharya, Aditi Kumari, Poulami Dutta, Ishita Gupta "Comparative study of Surface Potential for non conventional Double Gate MOSFETs", International Journal of VLSI Design and Technology, Journalspub, vol. 1, issue 1, pp. 1-19, 2018

20. Swapnadip De, Aditi Kumari, Poulami Dutta, Ishita Gupta, Mainak Bhattacharya, "A Review of Subthreshold Surface Potential for Single Gate Dual Material Double Halo MOSFET", International Journal of VLSI Design and Technology, Journalspub, vol. 2, issue 1, pp. 1-20, 2018, to be indexed in www.googlescholar.com